Embedded

Asynchronous reset synchronization and distribution – ASICs and FPGAs

Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...
Semiconductor Engineering

Speeding Up Timing Constraint Creation, Refinement And Validation

We are dealing with designs integrating many features and working with cutting-edge process technologies. Design methodologies and the design and process complexities can be overwhelming. To leverage ...
Embedded

Asynchronous reset synchronization and distribution – Special cases

Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...
Semiconductor Engineering

Experts At The Table: Timing Constraints

Low-Power Engineering sat down to discuss timing constraints with ARM Fellow David Flynn; Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys; Michael Carrell, ...
EDN

Resets in FPGA & ASIC control and data paths

Reset is an important mechanism to bring a digital system into a known state. The need for reset is governed by the system design and application, and various data and control paths are designed to ...
EDN

Global approach to timing margins and constraint definition for SoC design, Part 2

Margins related to OCV have to be added to the above-described inducing jitter phenomena. It is important to remember that the first phenomena—margins related to OCV– are always impacting both hold ...